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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 2780503002: MIPS[64]: Support for some SIMD operations (2) (Closed)
Patch Set: rebased Created 3 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 120 matching lines...) Expand 10 before | Expand all | Expand 10 after
131 V(MipsStoreToStackSlot) \ 131 V(MipsStoreToStackSlot) \
132 V(MipsByteSwap32) \ 132 V(MipsByteSwap32) \
133 V(MipsStackClaim) \ 133 V(MipsStackClaim) \
134 V(MipsSeb) \ 134 V(MipsSeb) \
135 V(MipsSeh) \ 135 V(MipsSeh) \
136 V(MipsS128Zero) \ 136 V(MipsS128Zero) \
137 V(MipsI32x4Splat) \ 137 V(MipsI32x4Splat) \
138 V(MipsI32x4ExtractLane) \ 138 V(MipsI32x4ExtractLane) \
139 V(MipsI32x4ReplaceLane) \ 139 V(MipsI32x4ReplaceLane) \
140 V(MipsI32x4Add) \ 140 V(MipsI32x4Add) \
141 V(MipsI32x4Sub) 141 V(MipsI32x4Sub) \
142 V(MipsF32x4Splat) \
143 V(MipsF32x4ExtractLane) \
144 V(MipsF32x4ReplaceLane) \
145 V(MipsF32x4SConvertI32x4) \
146 V(MipsF32x4UConvertI32x4)
142 147
143 // Addressing modes represent the "shape" of inputs to an instruction. 148 // Addressing modes represent the "shape" of inputs to an instruction.
144 // Many instructions support multiple addressing modes. Addressing modes 149 // Many instructions support multiple addressing modes. Addressing modes
145 // are encoded into the InstructionCode of the instruction and tell the 150 // are encoded into the InstructionCode of the instruction and tell the
146 // code generator after register allocation which assembler method to call. 151 // code generator after register allocation which assembler method to call.
147 // 152 //
148 // We use the following local notation for addressing modes: 153 // We use the following local notation for addressing modes:
149 // 154 //
150 // R = register 155 // R = register
151 // O = register or stack slot 156 // O = register or stack slot
152 // D = double register 157 // D = double register
153 // I = immediate (handle, external, int32) 158 // I = immediate (handle, external, int32)
154 // MRI = [register + immediate] 159 // MRI = [register + immediate]
155 // MRR = [register + register] 160 // MRR = [register + register]
156 // TODO(plind): Add the new r6 address modes. 161 // TODO(plind): Add the new r6 address modes.
157 #define TARGET_ADDRESSING_MODE_LIST(V) \ 162 #define TARGET_ADDRESSING_MODE_LIST(V) \
158 V(MRI) /* [%r0 + K] */ \ 163 V(MRI) /* [%r0 + K] */ \
159 V(MRR) /* [%r0 + %r1] */ 164 V(MRR) /* [%r0 + %r1] */
160 165
161 166
162 } // namespace compiler 167 } // namespace compiler
163 } // namespace internal 168 } // namespace internal
164 } // namespace v8 169 } // namespace v8
165 170
166 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 171 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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