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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <stdlib.h> | 5 #include <stdlib.h> |
6 #include <cmath> | 6 #include <cmath> |
7 #include <cstdarg> | 7 #include <cstdarg> |
8 | 8 |
9 #if V8_TARGET_ARCH_ARM64 | 9 #if V8_TARGET_ARCH_ARM64 |
10 | 10 |
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1946 return TransactionSize::HalfWord; | 1946 return TransactionSize::HalfWord; |
1947 case 4: | 1947 case 4: |
1948 return TransactionSize::Word; | 1948 return TransactionSize::Word; |
1949 default: | 1949 default: |
1950 UNREACHABLE(); | 1950 UNREACHABLE(); |
1951 } | 1951 } |
1952 return TransactionSize::None; | 1952 return TransactionSize::None; |
1953 } | 1953 } |
1954 | 1954 |
1955 void Simulator::VisitLoadStoreAcquireRelease(Instruction* instr) { | 1955 void Simulator::VisitLoadStoreAcquireRelease(Instruction* instr) { |
1956 unsigned rs = instr->Rs(); | |
1957 unsigned rt = instr->Rt(); | 1956 unsigned rt = instr->Rt(); |
1958 unsigned rn = instr->Rn(); | 1957 unsigned rn = instr->Rn(); |
1959 LoadStoreAcquireReleaseOp op = static_cast<LoadStoreAcquireReleaseOp>( | 1958 LoadStoreAcquireReleaseOp op = static_cast<LoadStoreAcquireReleaseOp>( |
1960 instr->Mask(LoadStoreAcquireReleaseMask)); | 1959 instr->Mask(LoadStoreAcquireReleaseMask)); |
1961 int32_t is_acquire_release = instr->LoadStoreXAcquireRelease(); | 1960 int32_t is_acquire_release = instr->LoadStoreXAcquireRelease(); |
1962 int32_t is_not_exclusive = instr->LoadStoreXNotExclusive(); | 1961 int32_t is_exclusive = (instr->LoadStoreXNotExclusive() == 0); |
1963 int32_t is_load = instr->LoadStoreXLoad(); | 1962 int32_t is_load = instr->LoadStoreXLoad(); |
1964 int32_t is_pair = instr->LoadStoreXPair(); | 1963 int32_t is_pair = instr->LoadStoreXPair(); |
1965 USE(is_acquire_release); | 1964 USE(is_acquire_release); |
1966 USE(is_not_exclusive); | |
1967 USE(is_pair); | 1965 USE(is_pair); |
1968 DCHECK_NE(is_acquire_release, 0); | 1966 DCHECK_NE(is_acquire_release, 0); // Non-acquire/release unimplemented. |
1969 DCHECK_EQ(is_not_exclusive, 0); // Non exclusive unimplemented. | 1967 DCHECK_EQ(is_pair, 0); // Pair unimplemented. |
1970 DCHECK_EQ(is_pair, 0); // Pair unimplemented. | |
1971 unsigned access_size = 1 << instr->LoadStoreXSizeLog2(); | 1968 unsigned access_size = 1 << instr->LoadStoreXSizeLog2(); |
1972 uintptr_t address = LoadStoreAddress(rn, 0, AddrMode::Offset); | 1969 uintptr_t address = LoadStoreAddress(rn, 0, AddrMode::Offset); |
1973 DCHECK(address % access_size == 0); | 1970 DCHECK_EQ(address % access_size, 0); |
1974 base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex); | 1971 base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex); |
1975 if (is_load != 0) { | 1972 if (is_load != 0) { |
1976 local_monitor_.NotifyLoadExcl(address, get_transaction_size(access_size)); | 1973 if (is_exclusive) { |
1977 global_monitor_.Pointer()->NotifyLoadExcl_Locked( | 1974 local_monitor_.NotifyLoadExcl(address, get_transaction_size(access_size)); |
1978 address, &global_monitor_processor_); | 1975 global_monitor_.Pointer()->NotifyLoadExcl_Locked( |
| 1976 address, &global_monitor_processor_); |
| 1977 } else { |
| 1978 local_monitor_.NotifyLoad(address); |
| 1979 } |
1979 switch (op) { | 1980 switch (op) { |
| 1981 case LDAR_b: |
1980 case LDAXR_b: | 1982 case LDAXR_b: |
1981 set_wreg_no_log(rt, MemoryRead<uint8_t>(address)); | 1983 set_wreg_no_log(rt, MemoryRead<uint8_t>(address)); |
1982 break; | 1984 break; |
| 1985 case LDAR_h: |
1983 case LDAXR_h: | 1986 case LDAXR_h: |
1984 set_wreg_no_log(rt, MemoryRead<uint16_t>(address)); | 1987 set_wreg_no_log(rt, MemoryRead<uint16_t>(address)); |
1985 break; | 1988 break; |
| 1989 case LDAR_w: |
1986 case LDAXR_w: | 1990 case LDAXR_w: |
1987 set_wreg_no_log(rt, MemoryRead<uint32_t>(address)); | 1991 set_wreg_no_log(rt, MemoryRead<uint32_t>(address)); |
1988 break; | 1992 break; |
1989 default: | 1993 default: |
1990 UNIMPLEMENTED(); | 1994 UNIMPLEMENTED(); |
1991 } | 1995 } |
1992 LogRead(address, access_size, rt); | 1996 LogRead(address, access_size, rt); |
1993 } else { | 1997 } else { |
1994 if (local_monitor_.NotifyStoreExcl(address, | 1998 if (is_exclusive) { |
1995 get_transaction_size(access_size)) && | 1999 unsigned rs = instr->Rs(); |
1996 global_monitor_.Pointer()->NotifyStoreExcl_Locked( | 2000 if (local_monitor_.NotifyStoreExcl(address, |
1997 address, &global_monitor_processor_)) { | 2001 get_transaction_size(access_size)) && |
| 2002 global_monitor_.Pointer()->NotifyStoreExcl_Locked( |
| 2003 address, &global_monitor_processor_)) { |
| 2004 switch (op) { |
| 2005 case STLXR_b: |
| 2006 MemoryWrite<uint8_t>(address, wreg(rt)); |
| 2007 break; |
| 2008 case STLXR_h: |
| 2009 MemoryWrite<uint16_t>(address, wreg(rt)); |
| 2010 break; |
| 2011 case STLXR_w: |
| 2012 MemoryWrite<uint32_t>(address, wreg(rt)); |
| 2013 break; |
| 2014 default: |
| 2015 UNIMPLEMENTED(); |
| 2016 } |
| 2017 LogWrite(address, access_size, rt); |
| 2018 set_wreg(rs, 0); |
| 2019 } else { |
| 2020 set_wreg(rs, 1); |
| 2021 } |
| 2022 } else { |
| 2023 local_monitor_.NotifyStore(address); |
| 2024 global_monitor_.Pointer()->NotifyStore_Locked(address, |
| 2025 &global_monitor_processor_); |
1998 switch (op) { | 2026 switch (op) { |
1999 case STLXR_b: | 2027 case STLR_b: |
2000 MemoryWrite<uint8_t>(address, wreg(rt)); | 2028 MemoryWrite<uint8_t>(address, wreg(rt)); |
2001 break; | 2029 break; |
2002 case STLXR_h: | 2030 case STLR_h: |
2003 MemoryWrite<uint16_t>(address, wreg(rt)); | 2031 MemoryWrite<uint16_t>(address, wreg(rt)); |
2004 break; | 2032 break; |
2005 case STLXR_w: | 2033 case STLR_w: |
2006 MemoryWrite<uint32_t>(address, wreg(rt)); | 2034 MemoryWrite<uint32_t>(address, wreg(rt)); |
2007 break; | 2035 break; |
2008 default: | 2036 default: |
2009 UNIMPLEMENTED(); | 2037 UNIMPLEMENTED(); |
2010 } | 2038 } |
2011 LogWrite(address, access_size, rt); | |
2012 set_wreg(rs, 0); | |
2013 } else { | |
2014 set_wreg(rs, 1); | |
2015 } | 2039 } |
2016 } | 2040 } |
2017 } | 2041 } |
2018 | 2042 |
2019 void Simulator::CheckMemoryAccess(uintptr_t address, uintptr_t stack) { | 2043 void Simulator::CheckMemoryAccess(uintptr_t address, uintptr_t stack) { |
2020 if ((address >= stack_limit_) && (address < stack)) { | 2044 if ((address >= stack_limit_) && (address < stack)) { |
2021 fprintf(stream_, "ACCESS BELOW STACK POINTER:\n"); | 2045 fprintf(stream_, "ACCESS BELOW STACK POINTER:\n"); |
2022 fprintf(stream_, " sp is here: 0x%016" PRIx64 "\n", | 2046 fprintf(stream_, " sp is here: 0x%016" PRIx64 "\n", |
2023 static_cast<uint64_t>(stack)); | 2047 static_cast<uint64_t>(stack)); |
2024 fprintf(stream_, " access was here: 0x%016" PRIx64 "\n", | 2048 fprintf(stream_, " access was here: 0x%016" PRIx64 "\n", |
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4163 processor->prev_ = nullptr; | 4187 processor->prev_ = nullptr; |
4164 processor->next_ = nullptr; | 4188 processor->next_ = nullptr; |
4165 } | 4189 } |
4166 | 4190 |
4167 #endif // USE_SIMULATOR | 4191 #endif // USE_SIMULATOR |
4168 | 4192 |
4169 } // namespace internal | 4193 } // namespace internal |
4170 } // namespace v8 | 4194 } // namespace v8 |
4171 | 4195 |
4172 #endif // V8_TARGET_ARCH_ARM64 | 4196 #endif // V8_TARGET_ARCH_ARM64 |
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