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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // | 2 // |
3 // Redistribution and use in source and binary forms, with or without | 3 // Redistribution and use in source and binary forms, with or without |
4 // modification, are permitted provided that the following conditions are | 4 // modification, are permitted provided that the following conditions are |
5 // met: | 5 // met: |
6 // | 6 // |
7 // * Redistributions of source code must retain the above copyright | 7 // * Redistributions of source code must retain the above copyright |
8 // notice, this list of conditions and the following disclaimer. | 8 // notice, this list of conditions and the following disclaimer. |
9 // * Redistributions in binary form must reproduce the above | 9 // * Redistributions in binary form must reproduce the above |
10 // copyright notice, this list of conditions and the following | 10 // copyright notice, this list of conditions and the following |
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1691 RecordRelocInfo(imm.rmode(), imm.value()); | 1691 RecordRelocInfo(imm.rmode(), imm.value()); |
1692 BlockConstPoolFor(1); | 1692 BlockConstPoolFor(1); |
1693 // The load will be patched when the constpool is emitted, patching code | 1693 // The load will be patched when the constpool is emitted, patching code |
1694 // expect a load literal with offset 0. | 1694 // expect a load literal with offset 0. |
1695 ldr_pcrel(rt, 0); | 1695 ldr_pcrel(rt, 0); |
1696 } | 1696 } |
1697 | 1697 |
1698 void Assembler::ldar(const Register& rt, const Register& rn) { | 1698 void Assembler::ldar(const Register& rt, const Register& rn) { |
1699 DCHECK(rn.Is64Bits()); | 1699 DCHECK(rn.Is64Bits()); |
1700 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAR_w : LDAR_x; | 1700 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAR_w : LDAR_x; |
1701 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1701 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1702 } | 1702 } |
1703 | 1703 |
1704 void Assembler::ldaxr(const Register& rt, const Register& rn) { | 1704 void Assembler::ldaxr(const Register& rt, const Register& rn) { |
1705 DCHECK(rn.Is64Bits()); | 1705 DCHECK(rn.Is64Bits()); |
1706 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAXR_w : LDAXR_x; | 1706 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAXR_w : LDAXR_x; |
1707 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1707 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1708 } | 1708 } |
1709 | 1709 |
1710 void Assembler::stlr(const Register& rt, const Register& rn) { | 1710 void Assembler::stlr(const Register& rt, const Register& rn) { |
1711 DCHECK(rn.Is64Bits()); | 1711 DCHECK(rn.Is64Bits()); |
1712 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLR_w : STLR_x; | 1712 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLR_w : STLR_x; |
1713 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1713 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1714 } | 1714 } |
1715 | 1715 |
1716 void Assembler::stlxr(const Register& rs, const Register& rt, | 1716 void Assembler::stlxr(const Register& rs, const Register& rt, |
1717 const Register& rn) { | 1717 const Register& rn) { |
1718 DCHECK(rs.Is32Bits()); | 1718 DCHECK(rs.Is32Bits()); |
1719 DCHECK(rn.Is64Bits()); | 1719 DCHECK(rn.Is64Bits()); |
1720 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLXR_w : STLXR_x; | 1720 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLXR_w : STLXR_x; |
1721 Emit(op | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1721 Emit(op | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1722 } | 1722 } |
1723 | 1723 |
1724 void Assembler::ldarb(const Register& rt, const Register& rn) { | 1724 void Assembler::ldarb(const Register& rt, const Register& rn) { |
1725 DCHECK(rt.Is32Bits()); | 1725 DCHECK(rt.Is32Bits()); |
1726 DCHECK(rn.Is64Bits()); | 1726 DCHECK(rn.Is64Bits()); |
1727 Emit(LDAR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1727 Emit(LDAR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1728 } | 1728 } |
1729 | 1729 |
1730 void Assembler::ldaxrb(const Register& rt, const Register& rn) { | 1730 void Assembler::ldaxrb(const Register& rt, const Register& rn) { |
1731 DCHECK(rt.Is32Bits()); | 1731 DCHECK(rt.Is32Bits()); |
1732 DCHECK(rn.Is64Bits()); | 1732 DCHECK(rn.Is64Bits()); |
1733 Emit(LDAXR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1733 Emit(LDAXR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1734 } | 1734 } |
1735 | 1735 |
1736 void Assembler::stlrb(const Register& rt, const Register& rn) { | 1736 void Assembler::stlrb(const Register& rt, const Register& rn) { |
1737 DCHECK(rt.Is32Bits()); | 1737 DCHECK(rt.Is32Bits()); |
1738 DCHECK(rn.Is64Bits()); | 1738 DCHECK(rn.Is64Bits()); |
1739 Emit(STLR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1739 Emit(STLR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1740 } | 1740 } |
1741 | 1741 |
1742 void Assembler::stlxrb(const Register& rs, const Register& rt, | 1742 void Assembler::stlxrb(const Register& rs, const Register& rt, |
1743 const Register& rn) { | 1743 const Register& rn) { |
1744 DCHECK(rs.Is32Bits()); | 1744 DCHECK(rs.Is32Bits()); |
1745 DCHECK(rt.Is32Bits()); | 1745 DCHECK(rt.Is32Bits()); |
1746 DCHECK(rn.Is64Bits()); | 1746 DCHECK(rn.Is64Bits()); |
1747 Emit(STLXR_b | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1747 Emit(STLXR_b | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1748 } | 1748 } |
1749 | 1749 |
1750 void Assembler::ldarh(const Register& rt, const Register& rn) { | 1750 void Assembler::ldarh(const Register& rt, const Register& rn) { |
1751 DCHECK(rt.Is32Bits()); | 1751 DCHECK(rt.Is32Bits()); |
1752 DCHECK(rn.Is64Bits()); | 1752 DCHECK(rn.Is64Bits()); |
1753 Emit(LDAR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1753 Emit(LDAR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1754 } | 1754 } |
1755 | 1755 |
1756 void Assembler::ldaxrh(const Register& rt, const Register& rn) { | 1756 void Assembler::ldaxrh(const Register& rt, const Register& rn) { |
1757 DCHECK(rt.Is32Bits()); | 1757 DCHECK(rt.Is32Bits()); |
1758 DCHECK(rn.Is64Bits()); | 1758 DCHECK(rn.Is64Bits()); |
1759 Emit(LDAXR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1759 Emit(LDAXR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1760 } | 1760 } |
1761 | 1761 |
1762 void Assembler::stlrh(const Register& rt, const Register& rn) { | 1762 void Assembler::stlrh(const Register& rt, const Register& rn) { |
1763 DCHECK(rt.Is32Bits()); | 1763 DCHECK(rt.Is32Bits()); |
1764 DCHECK(rn.Is64Bits()); | 1764 DCHECK(rn.Is64Bits()); |
1765 Emit(STLR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1765 Emit(STLR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1766 } | 1766 } |
1767 | 1767 |
1768 void Assembler::stlxrh(const Register& rs, const Register& rt, | 1768 void Assembler::stlxrh(const Register& rs, const Register& rt, |
1769 const Register& rn) { | 1769 const Register& rn) { |
1770 DCHECK(rs.Is32Bits()); | 1770 DCHECK(rs.Is32Bits()); |
1771 DCHECK(rt.Is32Bits()); | 1771 DCHECK(rt.Is32Bits()); |
1772 DCHECK(rn.Is64Bits()); | 1772 DCHECK(rn.Is64Bits()); |
1773 Emit(STLXR_h | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1773 Emit(STLXR_h | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1774 } | 1774 } |
1775 | 1775 |
1776 void Assembler::mov(const Register& rd, const Register& rm) { | 1776 void Assembler::mov(const Register& rd, const Register& rm) { |
1777 // Moves involving the stack pointer are encoded as add immediate with | 1777 // Moves involving the stack pointer are encoded as add immediate with |
1778 // second operand of zero. Otherwise, orr with first operand zr is | 1778 // second operand of zero. Otherwise, orr with first operand zr is |
1779 // used. | 1779 // used. |
1780 if (rd.IsSP() || rm.IsSP()) { | 1780 if (rd.IsSP() || rm.IsSP()) { |
1781 add(rd, rm, 0); | 1781 add(rd, rm, 0); |
1782 } else { | 1782 } else { |
1783 orr(rd, AppropriateZeroRegFor(rd), rm); | 1783 orr(rd, AppropriateZeroRegFor(rd), rm); |
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3218 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); | 3218 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); |
3219 DCHECK((target_offset >> 48) == 0); | 3219 DCHECK((target_offset >> 48) == 0); |
3220 add(rd, rd, scratch); | 3220 add(rd, rd, scratch); |
3221 } | 3221 } |
3222 | 3222 |
3223 | 3223 |
3224 } // namespace internal | 3224 } // namespace internal |
3225 } // namespace v8 | 3225 } // namespace v8 |
3226 | 3226 |
3227 #endif // V8_TARGET_ARCH_ARM64 | 3227 #endif // V8_TARGET_ARCH_ARM64 |
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