| Index: src/compiler/mips64/code-generator-mips64.cc
|
| diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
|
| index 4f1c59869e5cb7ebc6cf984a9b34b199ad8530dd..e06e165b5b0a7e6c78da0a6340b29b57a878a967 100644
|
| --- a/src/compiler/mips64/code-generator-mips64.cc
|
| +++ b/src/compiler/mips64/code-generator-mips64.cc
|
| @@ -1932,6 +1932,45 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| __ Assert(eq, static_cast<BailoutReason>(i.InputOperand(2).immediate()),
|
| i.InputRegister(0), Operand(i.InputRegister(1)));
|
| break;
|
| + case kMips64S128Zero: {
|
| + CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
|
| + __ xor_v(i.OutputSimd128Register(), i.OutputSimd128Register(),
|
| + i.OutputSimd128Register());
|
| + break;
|
| + }
|
| + case kMips64I32x4Splat: {
|
| + CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
|
| + __ fill_w(i.OutputSimd128Register(), i.InputRegister(0));
|
| + break;
|
| + }
|
| + case kMips64I32x4ExtractLane: {
|
| + CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
|
| + __ copy_s_w(i.OutputRegister(), i.InputSimd128Register(0),
|
| + i.InputInt8(1));
|
| + break;
|
| + }
|
| + case kMips64I32x4ReplaceLane: {
|
| + CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
|
| + Simd128Register src = i.InputSimd128Register(0);
|
| + Simd128Register dst = i.OutputSimd128Register();
|
| + if (!src.is(dst)) {
|
| + __ move_v(dst, src);
|
| + }
|
| + __ insert_w(dst, i.InputInt8(1), i.InputRegister(2));
|
| + break;
|
| + }
|
| + case kMips64I32x4Add: {
|
| + CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
|
| + __ addv_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| + break;
|
| + }
|
| + case kMips64I32x4Sub: {
|
| + CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
|
| + __ subv_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| + break;
|
| + }
|
| }
|
| return kSuccess;
|
| } // NOLINT(readability/fn_size)
|
|
|